Title: Network limits for time synchronisation in packet networks
Summary
Defines the reference model for the packet synchronization network assuming full timing support
Defines network limits and time accuracy budgets at each point
Describes hypothetical reference models of the packet network
Status
- Current version: 2nd3rd. Edition, October 2017, plus Amd. 1, March 2018November 2022 (latest version consented in April 2023)
- Download from: http://www.itu.int/ITU-T/recommendations/rec.aspx?rec=13323
- Enhancements in progress: definition of network limits for chains of enhanced (Class C, D) T-BCs
Key Contents
Network Limit at point C (network output) (clause 7.3.1):
Network Limit at point C (network output) (clause 7.3.2, enhanced syncE and class C clocks):
Example Network Design Budget (Appendix V):
| Budget component | Example budget | |
|---|---|---|
| PRTC | 100ns | |
| Random error (dTE) | 200ns | |
| Node error (cTE) | Type A: 550ns | Type B: 420ns |
| Link asymmetry (cTE) | 250ns | 380ns |
| Network limit point C | 1100ns | |
| Holdover in end app. | 250ns | |
| End application | 150ns | |
| Total limit at point E | 1500ns | |
Hypothetical Reference Model (HRM):
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| Table of Contents |
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